为了简化,所有的应用层协议数据都控制在 节点复位帧后,从节点置为复位状态(Reset State)。 处于复位状态的从节点在总线空闲时发送识别帧,待31个字节以内。
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Release ADC3 from reset state 解除ADC3复位状态
Release ADC1 from reset state 解除ADC1复位状态
Release ADC2 from reset state 解除ADC2复位状态
Release DAC from reset state 解除DAC复位状态
Enable DAC reset state 使能DAC复位状态
Enable SPI1 reset state 使能SPI1复位状态
Enable SPI2 reset state 使能SPI2复位状态
Enable SPI3 reset state 使能SPI3复位状态
Enable ADC1 reset state 允许ADC1复位状态
In order to test the circuits that has not any reset state, special way for resolving start state is described.
基于无复位时序电路,详细研究了有复位状态的同步电路测试生成问题及在无复位电路中的应用。
The reset state of a bit line is canceled when selected and connected to a read circuit for read, and information stored in a selected memory cell is read via the selected bit line.
当选择并且连接到用来读取的读取电路时,取消位线的复位状态并且通过所选的位线读取存储在所选存储器单元中的信息。
In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation.
在用于对读取周期中读取位线上的剩余电荷放电的半导体存储器装置中,位线在除读取操作期间以外的全部时间均处于复位状态。
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